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cmos 8-bit single chip microcomputer description the cxp83620/83624 and the cxp83621/83625 are cmos 8-bit single chip microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time-base timer, sub timer/counter, lcd controller/driver and remote control reception circuit besides the basic configurations of 8-bit cpu, rom, ram, and i/o port. the cxp83620/83624 and the cxp83621/83625 also provide a sleep/stop function that enables lower power consumption. features wide-range instruction system (213 instructions) to cover various types of data. ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 400ns at 10mhz operation (4.5 to 5.5v) 1s at 4mhz operation (2.7 to 5.5v) 122s at 32khz operation (2.7 to 5.5v) incorporated rom capacity 20k bytes (cxp83620, 83621) 24k bytes (cxp83624, 83625) incorporated ram capacity 736 bytes (includes lcd display data area and serial interface ram) peripheral functions ?a/d converter 8-bit, 8-channel, successive approximation method (conversion time of 12.4s/10mhz) ?serial interface incorporated buffer ram (auto transfer for 1 to 32 bytes), 1 channel 8-bit clock synchronized type (msb/lsb first selectable), 1 channel ?timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer, sub timer/counter ?lcd controller/driver maximum 128 segment display possible (during 1/4 duty) 4 common output, 32 segment output display method static, 1/2, 1/3, 1/4 duty bias method 1/2, 1/3 bias ?remote control reception circuit 8-bit pulse measuring counter, 6-stage fifo interruption 14 factors, 14 vectors, multi-interruption possible standby mode sleep/stop package 80-pin plastic qfp/lqfp piggy/evaluation chip cxp83600 (cxp83620, 83624) cxp83601 (cxp83621, 83625) structure silicon gate cmos ic ?1 e98134b96 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxp83620/83624 cxp83621/83625 cxp83620/83624 80 pin qfp (plastic) 80 pin lqfp (plastic) cxp83621/83625 80 pin qfp (plastic)
? 2 cxp83620/83624, cxp83621/83625 x t a l a / d c o n v e r t e r r e m o c o n s e r i a l i n t e r f a c e u n i t ( c h 0 ) 8 - b i t t i m e r / c o u n t e r 0 8 - b i t t i m e r 1 f i f o b u f f e r r a m i n t e r r u p t c o n t r o l l e r s p c 7 0 0 c p u c o r e r o m 2 0 k / 2 4 k b y t e s p r e s c a l e r / t i m e - b a s e t i m e r s u b t i m e r / c o u n t e r r a m 7 3 6 b y t e s 8 a n 0 t o a n 7 r m c s i 0 s o 0 s i 1 s o 1 e c c s 0 s c k 0 s c k 1 i n t 0 i n t 1 i n t 2 i n t 3 t e x t x e x t a l v d d v s s p o r t c 8 p c 0 t o p c 7 p o r t h 1 p h 0 p o r t b 8 p b 0 t o p b 7 p o r t e 5 2 p e 0 t o p e 4 p e 5 t o p e 6 2 l c d c o n t r o l l e r / d r i v e r 3 2 s e g 0 t o s e g 3 1 4 c o m 0 t o c o m 3 v l v l c 1 v l c 2 p o r t a 8 p a 0 t o p a 7 p o r t d 8 p d 0 t o p d 7 p o r t f 8 p f 0 t o p f 7 v l c 3 a d j t o c l o c k g e n e r a t o r / s y s t e m c o n t r o l r s t 3 i n t 4 p o r t i 2 p i 0 t o p i 1 s e r i a l i n t e r f a c e u n i t ( c h 1 ) block diagram
? 3 cxp83620/83624, cxp83621/83625 p e 3 / i n t 3 p e 4 / r m c p e 5 / t o p e 6 / a d j p b 0 p b 1 / c s 0 p b 2 / s c k 0 p b 3 / s i 0 p b 4 / s o 0 p b 5 / s c k 1 p b 6 / s i 1 p b 7 / s o 1 p c 0 p c 1 p c 2 p c 3 p c 4 p c 5 p c 6 p c 7 p h 0 / i n t 4 p a 0 / a n 0 p a 1 / a n 1 p a 2 / a n 2 p d 6 / s e g 2 2 p d 5 / s e g 2 1 p d 4 / s e g 2 0 p d 3 / s e g 1 9 p d 2 / s e g 1 8 p d 1 / s e g 1 7 p d 0 / s e g 1 6 s e g 1 5 s e g 1 4 s e g 1 3 s e g 1 2 s e g 1 1 s e g 1 0 s e g 9 s e g 8 s e g 7 s e g 6 s e g 5 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 c o m 3 p a 3 / a n 3 p a 4 / a n 4 p a 5 / a n 5 p a 6 / a n 6 p a 7 / a n 7 r s t e x t a l x t a l v s s v l v l c 3 v l c 2 v l c 1 c o m 0 c o m 1 c o m 2 p e 2 / i n t 2 p e 1 / i n t 1 p e 0 / i n t 0 / e c p f 7 / s e g 3 1 p f 6 / s e g 3 0 n c p i 1 / t e x p i 0 / t x v d d p f 5 / s e g 2 9 p f 4 / s e g 2 8 p f 3 / s e g 2 7 p f 2 / s e g 2 6 p f 1 / s e g 2 5 p f 0 / s e g 2 4 p d 7 / s e g 2 3 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 7 0 6 9 6 8 6 7 6 5 6 6 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 1 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 note) do not make any connections to nc (pin 75). pin assignment (top view) cxp83620/83624 (qfp package)
? 4 cxp83620/83624, cxp83621/83625 pin assignment (top view) cxp83620/83624 (lqfp package) p e 5 / t o p e 6 / a d j p b 0 p b 1 / c s 0 p b 2 / s c k 0 p b 3 / s i 0 p b 4 / s o 0 p b 5 / s c k 1 p b 6 / s i 1 p b 7 / s o 1 p c 0 p c 1 p c 2 p c 3 p c 4 p c 5 p c 6 p c 7 p h 0 / i n t 4 p a 0 / a n 0 p d 4 / s e g 2 0 p d 3 / s e g 1 9 p d 2 / s e g 1 8 p d 1 / s e g 1 7 p d 0 / s e g 1 6 s e g 1 5 s e g 1 4 s e g 1 3 s e g 1 2 s e g 1 1 s e g 1 0 s e g 9 s e g 8 s e g 7 s e g 6 s e g 5 s e g 4 s e g 3 s e g 2 s e g 1 p a 1 / a n 1 p a 2 / a n 2 p a 3 / a n 3 p a 4 / a n 4 p a 5 / a n 5 p a 6 / a n 6 p a 7 / a n 7 r s t e x t a l x t a l v s s v l v l c 3 v l c 2 v l c 1 c o m 0 c o m 1 c o m 2 c o m 3 s e g 0 p e 4 / r m c p e 3 / i n t 3 p e 2 / i n t 2 p e 1 / i n t 1 p e 0 / i n t 0 / e c p f 7 / s e g 3 1 p f 6 / s e g 3 0 n c p i 1 / t e x p i 0 / t x v d d p f 5 / s e g 2 9 p f 4 / s e g 2 8 p f 3 / s e g 2 7 p f 2 / s e g 2 6 p f 1 / s e g 2 5 p f 0 / s e g 2 4 p d 7 / s e g 2 3 p d 6 / s e g 2 2 p d 5 / s e g 2 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 7 0 6 9 6 8 6 7 6 5 6 6 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 1 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 note) do not make any connections to nc (pin 73).
? 5 cxp83620/83624, cxp83621/83625 pin assignment (top view) cxp83621/83625 (qfp package) p e 5 / t o p e 6 / a d j p b 0 p b 1 / c s 0 p b 2 / s c k 0 p b 3 / s i 0 p b 4 / s o 0 p b 5 / s c k 1 p b 6 / s i 1 p b 7 / s o 1 p c 0 p c 1 p c 2 p c 3 p c 4 p c 5 p c 6 p c 7 p h 0 / i n t 4 p a 0 / a n 0 p d 4 / s e g 2 0 p d 3 / s e g 1 9 p d 2 / s e g 1 8 p d 1 / s e g 1 7 p d 0 / s e g 1 6 s e g 1 5 s e g 1 4 s e g 1 3 s e g 1 2 s e g 1 1 s e g 1 0 s e g 9 s e g 8 s e g 7 s e g 6 s e g 5 s e g 4 s e g 3 s e g 2 s e g 1 p a 1 / a n 1 p a 2 / a n 2 p a 3 / a n 3 p a 4 / a n 4 p a 5 / a n 5 p a 6 / a n 6 p a 7 / a n 7 r s t e x t a l x t a l v s s v l v l c 3 v l c 2 v l c 1 c o m 0 c o m 1 c o m 2 c o m 3 s e g 0 p e 4 / r m c p e 3 / i n t 3 p e 2 / i n t 2 p e 1 / i n t 1 p e 0 / i n t 0 / e c p f 7 / s e g 3 1 p f 6 / s e g 3 0 n c p i 1 / t e x p i 0 / t x v d d p f 5 / s e g 2 9 p f 4 / s e g 2 8 p f 3 / s e g 2 7 p f 2 / s e g 2 6 p f 1 / s e g 2 5 p f 0 / s e g 2 4 p d 7 / s e g 2 3 p d 6 / s e g 2 2 p d 5 / s e g 2 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 7 0 6 9 6 8 6 7 6 5 6 6 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 1 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 note) do not make any connections to nc (pin 73).
? 6 cxp83620/83624, cxp83621/83625 pin description symbol i/o functions i/o/analog input pa0/an0 to pa7/an7 (port a) 8-bit i/o port. i/o can be set in a bit unit. standby release input can be set in a bit unit. incorporation of pull-up resistor can be set through the program in a bit unit. (8 pins) analog inputs to a/d converter. (8 pins) i/o pc0 to pc7 pe0/int0/ec pe1/int1 pe2/int2 pe3/int3 pe4/rmc pe5/to pe6/adj ph0/int4 pi0/tx pi1/tex input/input/input input/input input/input input/input input/input output/output output/output i/o/input input input/input (port c) 8-bit i/o port. i/o can be set in a bit unit. capable of driving 12ma sink current. incorporation of pull-up resistor can be set through the program in a bit unit. (8 pins) (port e) 7-bit port. lower 5 bits are for inputs; upper 2 bits are for outputs. (7 pins) (port h) 1-bit i/o port. incorporation of pull-up resistor can be set through the program. (1 pin) (port i) 2-bit input port. (2 pins) external interruption request input. (1 pin) crystal connectors for sub timer/counter clock oscillation. for usage as event counter, input to tex, and leave tx open. external event inputs for 8-bit timer/counter. external interruption request inputs. (4 pins) remote control reception circuit input. output for 8-bit timer/counter rectangular wave. output for tex oscillation frequency division. i/o i/o/input i/o/i/o i/o/input i/o/output i/o/i/o i/o/input i/o/output pb0 pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 (port b) 8-bit i/o port. i/o can be set in a bit unit. incorporation of pull-up resistor can be set through the program in a bit unit. (8 pins) chip select input for serial interface (ch0). serial clock i/o (ch0). serial data input (ch0). serial data output (ch0). serial clock i/o (ch1). serial data input (ch1). serial data output (ch1).
? 7 cxp83620/83624, cxp83621/83625 symbol i/o functions output/output pf0/seg24 to pf7/seg31 (port f) 8-bit output port. (8 pins) output/output pd0/seg16 to pd7/seg23 (port d) 8-bit output port. (8 pins) output seg0 to seg15 lcd segment signal output. (16 pins) input crystal connectors for system clock oscillation. when the clock is supplied externally, input to extal; opposite phase clock should be input to xtal. extal output com0 to com3 lcd common signal output. (4 pins) v lc1 to v lc3 lcd bias power supply. (3 pins) output v l control pin to cut off the current flowing to external lcd bias resistor during standby. xtal input low-level active system reset. nc. do not make any connections to nc. positive power supply. gnd. rst nc v dd v ss lcd segment signal outputs. (16 pins)
? 8 cxp83620/83624, cxp83621/83625 * p u l l - u p t r a n s i s t o r a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) i p p u l l - u p r e s i s t o r p o r t b d a t a p o r t b d i r e c t i o n " 0 " a f t e r a r e s e t r d ( p o r t b ) " 0 " a f t e r a r e s e t * i n t e r n a l d a t a b u s * p u l l - u p t r a n s i s t o r a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) i p p u l l - u p r e s i s t o r p o r t b d a t a p o r t b d i r e c t i o n " 0 " a f t e r a r e s e t r d ( p o r t b ) " 0 " a f t e r a r e s e t * i n t e r n a l d a t a b u s c s 0 s i 0 s i 1 s c h m i t t i n p u t port b 8 pins hi-z hi-z after a reset pa0/an0 to pa7/an7 pb0 port b 1 pin 3 pins hi-z pb1/cs0 pb3/si0 pb6/si1 * p u l l - u p t r a n s i s t o r a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) i p p u l l - u p r e s i s t o r p o r t a d a t a p o r t a d i r e c t i o n " 0 " a f t e r a r e s e t p o r t a f u n c t i o n s e l e c t " 0 " a f t e r a r e s e t r d ( p o r t a ) a / d c o n v e r t e r i n p u t m u l t i p l e x e r " 0 " a f t e r a r e s e t i n p u t p r o t e c t i o n c i r c u i t * e d g e d e t e c t i o n c i r c u i t i n t e r n a l d a t a b u s s t a n d b y r e l e a s e i/o circuit format for pins port a pin circuit format
? 9 cxp83620/83624, cxp83621/83625 p u l l - u p r e s i s t o r " 0 " a f t e r a r e s e t r d ( p o r t b ) * " 0 " a f t e r a r e s e t i n t e r n a l d a t a b u s p o r t b d a t a p o r t b d i r e c t i o n i p s e r i a l d a t a o u t p u t e b a b l e p o r t b f u n c t i o n s e l e c t " 0 " a f t e r a r e s e t s o " 0 " a f t e r a r e s e t * p u l l - u p t r a n s i s t o r a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) o u t p u t b u f f e r c a p a b i l i t y port b port c 2 pins hi-z hi-z after a reset pb2/sck0 pb5/sck1 pb4/so0 pb7/so1 2 pins hi-z pc0 to pc7 8 pins p u l l - u p r e s i s t o r " 0 " a f t e r a r e s e t r d ( p o r t b ) * " 0 " a f t e r a r e s e t s c h m i t t i n p u t s c k i n i n t e r n a l d a t a b u s p o r t b d a t a p o r t b d i r e c t i o n i p s e r i a l c l o c k o u t p u t e b a b l e p o r t b f u n c t i o n s e l e c t " 0 " a f t e r a r e s e t s c k o u t " 0 " a f t e r a r e s e t * p u l l - u p t r a n s i s t o r a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) o u t p u t b u f f e r c a p a b i l i t y port b pin circuit format i p p u l l - u p r e s i s t o r p o r t c d a t a p o r t c d i r e c t i o n " 0 " a f t e r a r e s e t r d ( p o r t c ) " 0 " a f t e r a r e s e t * 2 i n t e r n a l d a t a b u s * 1 * 2 p u l l - u p t r a n s i s t o r a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) * 1 h i g h c u r r e n t d r i v e 1 2 m a ( v d d = 4 . 5 t o 5 . 5 v ) 4 . 5 m a ( v d d = 2 . 7 t o 3 . 3 v )
? 10 cxp83620/83624, cxp83621/83625 p o r t e f u n c t i o n s e l e c t r d ( p o r t e ) i n t e r n a l d a t a b u s " 0 " a f t e r a r e s e t p o r t e d a t a " 1 " a f t e r a r e s e t t o port e port e port h 5 pins hi-z high level after a reset pe0/int0/ec pe1/int1 pe2/int2 pe3/int3 pe4/rmc pe5/to 1 pin pe6/adj 1 pin hi-z ph0/int4 1 pin i p s c h m i t t i n p u t i n t 0 / e c i n t 1 i n t 2 i n t 3 r m c i n t e r n a l d a t a b u s r d ( p o r t e ) port e pin circuit format p o r t e d a t a " 1 " a f t e r a r e s e t m p x a d j 2 k a d j 1 6 k a d j 3 2 k i n t e r n a l r e s e t s i g n a l * 2 * 1 a d j s i g n a l s a r e f r e q u e n c y d r i v e r o u t p u t s f o r t e x o s c i l l a t i o n f r e q u e n c y a d j u s t m e n t . a d j 2 k p r o v i d e s u s a g e a s b u z z e r o u t p u t . * 2 p u l l - u p t r a n s i s t o r a p p r o x . 1 5 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 2 0 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) * 1 p o r t e f u n c t i o n s e l e c t ( u p p e r ) p o r t e f u n c t i o n s e l e c t ( l o w e r ) r d ( p o r t e ) i n t e r n a l d a t a b u s 0 0 " 0 0 " a f t e r a r e s e t 0 1 1 0 1 1 * p u l l - u p t r a n s i s t o r a p p r o x . 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x . 1 5 0 k w ( v d d = 2 . 7 t o 3 . 3 v ) i p p u l l - u p r e s i s t o r p o r t h d a t a p o r t h d i r e c t i o n " 0 " a f t e r a r e s e t r d ( p o r t h ) " 0 " a f t e r a r e s e t * i n t e r n a l d a t a b u s i n t 4 s c h m i t t i n p u t high level high level at on resistance of pull-up transistor during a reset.
? 11 cxp83620/83624, cxp83621/83625 s e g m e n t d a t a s e g m e n t d r i v e r p o r t / s e g m e n t o u t p u t s e l e c t " 0 " a f t e r a r e s e t p o r t d , f d a t a port d port f segment common 2 pins oscillation halted port input segment output (v dd level) after a reset pi0/tx pi1/tex pd0/seg16 to pd7/seg23 pf0/seg24 to pf7/seg31 16 pins v dd level seg0 to seg15 16 pins v dd level com0 to com3 4 pins " 1 " a f t e r a r e s e t r d ( p o r t i ) i n t e r n a l d a t a b u s s c h m i t t i n p u t i p i p r d ( p o r t i ) i n t e r n a l d a t a b u s c l o c k i n p u t p i 1 / t e x p i 0 / t x t e x o s c i l l a t i o n c o n t r o l c i r c u i t port i pin circuit format v c h v c l v l c 1 v l c 2 v l c 3 v d d
? 12 cxp83620/83624, cxp83621/83625 e x t a l x t a l i p i p d i a g r a m s h o w s c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . f e e d b a c k r e s i s t o r i s r e m o v e d d u r i n g s t o p . x t a l b e c o m e s h i g h l e v e l . 1 pin hi-z oscillation after a reset v l extal xtal 2 pins low level (during a reset) rst 1 pin l c d c o n t r o l ( d s p b i t ) " 0 " a f t e r a r e s e t pin circuit format i p s c h m i t t i n p u t m a s k o p t i o n p u l l - u p r e s i s t o r a o p
? 13 cxp83620/83624, cxp83621/83625 * 1 v in and v out must not exceed v dd + 0.3v. * 2 the high current drive transistor is the n-ch transistor of port c (pc). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. supply voltage lcd bias voltage input voltage output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd v lc1 , v lc2 , v lc3 v in v out i oh s i oh i ol i olc s i ol topr tstg p d ?.3 to +7.0 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ? ?0 15 20 100 ?0 to +75 ?5 to +150 600 380 380 v v v v ma ma ma ma ma c c mw mw mw output per pin total for all output pins value per pin, excluding high current output pins value per pin for high current output pins * 2 total for all output pins qfp-80p-l01 lqfp-80p-l01 qfp-80p-l03 item symbol rating unit remarks absolute maximum ratings (vss = 0v)
? 14 cxp83620/83624, cxp83621/83625 lcd bias voltage high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v c v item symbol min. max. unit remarks 2.7 2.7 2.5 vss 0.7v dd 0.8v dd v dd ?0.4 0 0 ?.3 ?0 v lc1 v lc2 v lc3 v ih v ihs v ihex v il v ils v ilex topr guaranteed operation range during 1/16 frequency dividing mode or sleep mode guaranteed operation range with tex clock guaranteed data hold range during stop lcd power supply range * 4 * 1 hysteresis input * 2 extal * 3 , tex * 5 * 1 hysteresis input * 2 extal * 3 , tex * 5 v dd * 1 value for each pin of normal input ports (pa, pb0, pb4, pb7, pc and pi). * 2 value of the following pins; rst, cs0, si0, si1, sck0, sck1, ec/int0, int1, int2, int3, int4 and rmc. * 3 specifies only during external clock input. * 4 optimal values are determined by lcd used. * 5 specifies only during external event count input. recommended operating conditions (vss = 0v) guaranteed operation range during 1/2 and 1/4 frequency dividing mode fc = 10mhz or less fc = 4mhz or less 4.5 2.7 5.5 5.5
? 15 cxp83620/83624, cxp83621/83625 v dd = 4.5v, i oh = ?.0ma v dd = 4.5v, i oh = ?.4ma v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v v dd = 5.5v v il = 0.4v v dd = 4.5v, v ih = 4.0v v dd = 5.5v v i = 0, 5.5v v dd = 5v v lc1 = 3.75v v lc2 = 2.5v v lc3 = 1.25v high level output voltage i/o leakage current supply current * 5 4.0 3.5 4.0 3.5 0.5 ?.5 0.1 ?.1 ?.5 ?.78 v v v v v v v v a a a a a a a k k pc pa, pb, pc, pd * 2 , pe5, pe6, pf * 2 , ph0, v l (v ol only) sck0 * 1 , so0 * 1 sck1 * 1 , so1 * 1 extal tex rst * 3 item symbol pins conditions min. pa to pc * 4 , pe0 to pe4, ph * 4 , pi, rst * 3 v dd i iz common output impedance r com segment output impedance r seg com0 to com3 seg0 to seg15, seg16 to seg31 * 2 i dd1 high-speed mode operation (1/2 frequency dividing clock) i dds1 i dds3 v ol i ihe i ile i iht i ilt i ilr i il i ih low level output voltage input current 3 5 typ. 0.4 0.6 1.5 40 ?0 10 ?0 ?00 ?5 10 5 15 max. unit dc characteristics (v dd = 4.5 to 5.5v) electrical characteristics (ta = ?0 to +75 c, vss = 0v) v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) sleep mode stop mode v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) 12 40 ma 2.6 8 ma v dd = 5.5v, 10mhz and termination of tex oscillation 10 a v oh
? 16 cxp83620/83624, cxp83621/83625 * 1 specifies when port b output buffer capability switching register (bufb: 01f4h) selects the buffer capability to high. * 2 common pins of pd0/seg16 to pd7/seg23, pf0/seg24 to pf7/seg31, pd and pf is the case when the common pin is selected as port; seg16 to seg31 is when the common pin is selected as segment output. * 3 rst specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. * 4 pins pa to pc, and ph0 specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. * 5 when all output pins are left open. clock 1mhz 0v for all pins excluding measured pins input capacity 10 20 pf pa to pc, pe0 to pe4, ph, pi, extal, rst item symbol pins conditions min. c in typ. max. unit
? 17 cxp83620/83624, cxp83621/83625 v dd = 2.7v, i oh = ?.12ma v dd = 2.7v, i oh = ?.45ma v dd = 2.7v, i ol = 1.0ma v dd = 2.7v, i ol = 1.4ma v dd = 2.7v, i ol = 4.5ma v dd = 3.3v, v ih = 3.3v v dd = 3.3v, v il = 0.3v v dd = 3.3v, v ih = 3.3v v dd = 3.3v v il = 0.3v v dd = 2.7v, v ih = 2.4v v dd = 3.3v v i = 0, 3.3v v dd = 3v v lc1 = 2.25v v lc2 = 1.5v v lc3 = 0.75v high level output voltage i/o leakage current supply current * 5 2.5 2.1 0.3 ?.3 0.1 ?.1 ?.9 0.9 v v v v v v a a a a a a a k k pc pa, pb, pc, pd * 2 , pe5, pe6, pf * 2 , ph0, v l (v ol only) extal tex rst * 3 item symbol pins conditions min. pa to pc * 4 , pe0 to pe4, ph * 4 , pi, rst * 3 v dd i iz common output impedance r com segment output impedance r seg com0 to com3 seg0 to seg15, seg16 to seg31 * 2 i dd1 high-speed mode operation (1/2 frequency dividing clock) i dds1 i dds3 v oh v ol i ihe i ile i iht i ilt i ilr i il i ih low level output voltage input current 4.5 10 typ. 0.25 0.4 0.9 20 ?0 10 ?0 ?00 ?0 10 7.5 30 max. unit i dd2 dc characteristics (v dd = 2.7 to 3.3v) electrical characteristics (ta = ?0 to +75 c, vss = 0v) v dd = 3.3v, 4mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3.3v, tex * 6 crystal oscillation (c 1 = c 2 = 47pf) sleep mode stop mode v dd = 3.3v, 4mhz crystal oscillation (c 1 = c 2 = 15pf) 2.5 8 ma 30 100 a 0.6 2 ma i dds2 v dd = 3.3v, tex * 6 crystal oscillation (c 1 = c 2 = 47pf) v dd = 3.3v, 4mhz and termination of tex oscillation 16 30 a 10 a sck0 * 1 , so0 * 1 sck1 * 1 , so1 * 1 v dd = 2.7v, i oh = ?.24ma v dd = 2.7v, i oh = ?.90ma 2.5 v 2.1 v
? 18 cxp83620/83624, cxp83621/83625 * 1 specifies when port b output buffer capability switching register (bufb: 01f4h) selects the buffer capability to high. * 2 common pins of pd0/seg16 to pd7/seg23, pf0/seg24 to pf7/seg31, pd and pf is the case when the common pin is selected as port; seg16 to seg31 is when the common pin is selected as segment output. * 3 rst specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. * 4 pins pa to pc, and ph0 specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. * 5 when all output pins are left open. * 6 the value when 32.768khz oscillator is connected to tex. clock 1mhz 0v for all pins excluding measured pins input capacity 10 20 pf pa to pc, pe0 to pe4, ph, pi, extal, rst item symbol pins conditions min. c in typ. max. unit
? 19 cxp83620/83624, cxp83621/83625 * 1 t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (clc: 00feh). t sys [ns] = 2000/fc (upper two bits = ?0?, 4000/fc (upper two bits = ?1?, 16000/fc (upper two bits = ?1?. e x t a l t x h t x l t c f t c r 0 . 4 v v d d 0 . 4 v 1 / f c a a a a a a a a a a a a a a a a c r y s t a l o s c i l l a t i o n c e r a m i c o s c i l l a t i o n e x t a l x t a l e x t e r n a l c l o c k e x t a l x t a l 7 4 h c 0 4 c 1 c 2 a a a a a a a a t e x c l o c k a p p l i e d c o n d i t i o n c r y s t a l o s c i l l a t i o n t e x t x c 1 c 2 t e x e c t e h t e l t e f t e r 0 . 2 v d d 0 . 8 v d d t t h t t l t t f t t r ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise and fall time event count input clock pulse width event count input clock rise and fall time system clock frequency event count input clock input pulse width event count input clock rise and fall time f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal extal extal ec ec tex tx tex tex mhz ns ns ns ms khz s ms fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied condition) fig. 3 fig. 3 1 1 37.5 77.5 t sys + 50 * 1 10 32.768 10 5 200 20 20 (ta = ?0 to +75 c, v dd = 2.7 to 5.5v, vss = 0v) fig. 2. clock applied conditions fig. 1. clock timing fig. 3. event count clock timing item symbol pin conditions min. unit typ. max. v dd = 4.5 to 5.5v v dd = 4.5 to 5.5v
? 20 cxp83620/83624, cxp83621/83625 chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (clc: 00feh). t sys [ns] = 2000/fc (upper two bits = ?0?, 4000/fc (upper two bits = ?1?, 16000/fc (upper two bits = ?1? note 2) cs, sck, si and so indicates cs0, sck0, si0 and so0, respectively. note 3) the load condition for the sck output mode, so output delay time is 50pf + 1ttl. note 4) the value when port b output buffer capability switching register (bufb: 01f4h) selects buffer capability to normal. (2) serial transfer (ch0) (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item cs ? sck delay time cs - ? sck float delay time cs ? so delay time cs ? so float delay time cs high level width sck cycle time sck high and low level widths si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc ?100 t sys + 100 200 2 t sys + 100 100 ns ns ns ns ns ns ns ns ns ns 2 t sys + 200 100 max. unit conditions
? 21 cxp83620/83624, cxp83621/83625 chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (clc: 00feh). t sys [ns] = 2000/fc (upper two bits = ?0?, 4000/fc (upper two bits = ?1?, 16000/fc (upper two bits = ?1? note 2) cs, sck, si and so indicates cs0, sck0, si0 and so0, respectively. note 3) the load condition for the sck output mode, so output delay time is 50pf. note 4) the value when port b output buffer capability switching register (bufb: 01f4h) selects buffer capability to high. serial transfer (ch0) (ta = ?0 to +75 c, v dd = 2.7 to 3.3v, vss = 0v) item cs ? sck delay time cs - ? sck float delay time cs ? so delay time cs ? so float delay time cs high level width sck cycle time sck high and low level widths si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode ns ns ns ns ns symbol pin min. t sys + 250 t sys + 200 t sys + 250 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc ?150 t sys + 100 200 2 t sys + 100 100 ns ns ns ns ns ns ns ns ns ns 2 t sys + 250 125 max. unit conditions
? 22 cxp83620/83624, cxp83621/83625 fig. 4. serial transfer ch0 timing c s 0 s c k 0 0 . 2 v d d 0 . 8 v d d t w h c s t d c s k t d c s k f 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d t k c y t k l t k h 0 . 8 v d d 0 . 2 v d d s i 0 t s i k t k s i i n p u t d a t a t d c s o t k s o t d c s o f o u t p u t d a t a 0 . 8 v d d 0 . 2 v d d s o 0
? 23 cxp83620/83624, cxp83621/83625 serial transfer (ch1) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item sck cycle time t kcy sck1 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc ?50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns sck1 si1 si1 so1 t kh t kl t sik t ksi t kso sck high and low level widths si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time symbol pin conditions min. max. unit note 1) t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (clc: 00feh). t sys [ns] = 2000/fc (upper two bits = ?0?, 4000/fc (upper two bits = ?1?, 16000/fc (upper two bits = ?1? note 2) sck, si and so indicates sck1, si1 and so1, respectively. note 3) the load condition for the sck1 output mode, so1 output delay time is 50pf + 1ttl. note 4) the value when port b output buffer capability switching register (bufb: 01f4h) selects buffer capability to normal. serial transfer (ch1) (ta = 20 to +75 c, v dd = 2.7 to 3.3v, vss = 0v) item sck cycle time t kcy sck1 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc ?100 100 200 200 100 250 125 ns ns ns ns ns ns ns ns ns ns sck1 si1 si1 so1 t kh t kl t sik t ksi t kso sck high and low level widths si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time symbol pin conditions min. max. unit note 1) t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (clc: 00feh). t sys [ns] = 2000/fc (upper two bits = ?0?, 4000/fc (upper two bits = ?1?, 16000/fc (upper two bits = ?1? note 2) sck, si and so indicates sck1, si1 and so1, respectively. note 3) the load condition for the sck1 output mode, so1 output delay time is 50pf. note 4) the value when port b output buffer capability switching register (bufb: 01f4h) selects buffer capability to high.
? 24 cxp83620/83624, cxp83621/83625 t k c y t k l t k h 0 . 2 v d d 0 . 8 v d d t s i k t k s i t k s o i n p u t d a t a o u t p u t d a t a 0 . 2 v d d 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d s c k 1 s i 1 s o 1 fig. 5. serial transfer ch1 timing
? 25 cxp83620/83624, cxp83621/83625 conversion time sampling time analog input voltage t conv t samp v ian v zt * 1 v ft * 2 an0 to an7 ta = 25 c v dd = 5.0v v ss = 0v linearity error zero transition voltage full-scale transition voltage resolution s s v v dd 31/f adc * 3 10/f adc * 3 0 item symbol pin conditions min. typ. max. unit bits (3) a/d converter characteristics (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) 8 3 lsb 70 mv 5030 10 4970 ?0 4910 mv conversion time sampling time analog input voltage t conv t samp v ian v zt * 1 v ft * 2 an0 to an7 ta = 25 c v dd = 2.7v v ss = 0v linearity error zero transition voltage full-scale transition voltage resolution s s v v dd 31/f adc * 3 10/f adc * 3 0 item symbol pin conditions min. typ. max. unit bits (ta = ?0 to +75 c, v dd = 2.7 to 3.3v, vss = 0v) 8 3 lsb 40 mv 2716 11 2688 ?0 2651 mv fig. 6. definition of a/d converter terms a n a l o g i n p u t l i n e a r i t y e r r o r v f t v z t 0 0 h 0 1 h f e h f f h d i g i t a l c o n v e r s i o n v a l u e * 1 v z t : v a l u e a t w h i c h t h e d i g i t a l c o n v e r s i o n v a l u e c h a n g e s f r o m 0 0 h t o 0 1 h a n d v i c e v e r s a . * 2 v f t : v a l u e a t w h i c h t h e d i g i t a l c o n v e r s i o n v a l u e c h a n g e s f r o m f e h t o f f h a n d v i c e v e r s a . * 3 f a d c = f c / 4
? 26 cxp83620/83624, cxp83621/83625 external interruption high and low level widths reset input low level width int0 int1 int2 int3 int4 rst 1 32/fc s s item symbol pin conditions min. max. unit t ih t il t rsl (4) interruption, reset input (ta = ?0 to +75 c, v dd = 2.7 to 5.5v, vss = 0v) 0 . 2 v d d 0 . 8 v d d t i h t i l t i l t i h i n t 0 i n t 1 i n t 2 i n t 3 i n t 4 fig. 7. interruption input timing t r s l 0 . 2 v d d r s t fig. 8. rst input timing
? 27 cxp83620/83624, cxp83621/83625 appendix c 1 a a a a a a a a e x t a l x t a l c 2 r d a a a a a a a a e x t a l x t a l ( i ) m a i n c l o c k a a a a a a a a e x t a l x t a l c 1 c 2 r d x t a l ( i i ) m a i n c l o c k a a a a a a a a e x t a l x t a l c 1 c 2 r d a a a a a a a a t e x t x ( i i i ) s u b c l o c k item content reset pin pull-up resistor non-existent existent mask option table product name package cxp83620/83624 cxp83621/83625 80-pin plastic qfp/lqfp 80-pin plastic qfp (0.65mm pitch) package list fig. 9. spc700 series recommended oscillation circuit * 1 those marked with an * 1 signify types with built-in ground capacitance (c 1 , c 2 ). manufacturer murata mfg co., ltd. river eletec co., ltd. kinseki ltd. model csa4.19mg csa8.00mg cst4.19mgw * 1 cst8.00mtw * 1 hc-49/u03 cx-5f fcr4.19mc5 * 1 fcr8.0mc5 * 1 fcr10.0mc5 * 1 ccr4.19mc3 * 1 ccr8.0mc5 * 1 ccr10.0mc5 * 1 tdk corporation seiko instruments inc. vtc-200 sp-t fc (mhz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 32.768 75.00 c 1 (pf) c 2 (pf) rd ( ) 100 30 30 100 30 30 22 15 10 33 18 15 30 ( 20%) 20 ( 20%) 20 ( 20%) 36 ( 20%) 20 ( 20%) 20 ( 20%) 18 4 100 30 30 100 30 30 22 15 10 33 18 15 30( 20%) 20( 20%) 20( 20%) 36( 20%) 20( 20%) 20( 20%) 18 4 0 0 0 0 0 0 1.0k 100 100 2.2k 0 0 0 330k 100k circuit example (i) csa10.0mt (ii) cst10.00mtw * 1 (i) (ii) (iii) remarks cl = 12.5pf cl = 6.0pf fcr *** : lead-type ceramic oscillator ccr *** : surface mounted-type ceramic oscillator cl : load capacitor cl = 12.0pf cl = 12.0pf cl = 12.0pf
? 28 cxp83620/83624, cxp83621/83625 1 0 . 0 1 . 0 0 . 1 ( 1 0 0 a ) 0 . 0 1 ( 1 0 a ) 1 2 3 4 5 6 7 i d d v s . v d d ( f c = 1 0 m h z , t a = 2 5 c , t y p i c a l ) v d d s u p p l y v o l t a g e [ v ] i d d s u p p l y c u r r e n t [ m a ] 5 . 0 0 . 5 0 . 0 5 ( 5 0 a ) 1 / 1 6 f r e q u e n c y d i v i d i n g m o d e s l e e p m o d e 1 / 4 f r e q u e n c y d i v i d i n g m o d e 1 / 2 f r e q u e n c y d i v i d i n g m o d e 3 2 k h z m o d e ( i n s t r u c t i o n ) 3 2 k h z s l e e p m o d e 0 5 1 0 0 5 1 0 1 5 1 / 2 f r e q u e n c y d i v i d i n g m o d e 1 / 4 f r e q u e n c y d i v i d i n g m o d e 1 / 1 6 f r e q u e n c y d i v i d i n g m o d e s l e e p m o d e i d d v s . f c ( v d d = 5 v , t a = 2 5 c , t y p i c a l ) f c s y s t e m c l o c k [ m h z ] i d d s u p p l y c u r r e n t [ m a ] characteristics curve
? 29 cxp83620/83624, cxp83621/83625 package outline unit: mm cxp83620/83624 p a c k a g e s t r u c t u r e s o n y c o d e e i a j c o d e j e d e c c o d e q f p - 8 0 p - l 0 1 q f p 0 8 0 - p - 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y 1 . 6 g 2 3 . 9 0 . 4 2 0 . 0 0 . 1 + 0 . 4 1 8 0 6 5 6 4 4 1 4 0 2 5 2 4 0 . 8 0 . 3 5 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 + 0 . 4 1 7 . 9 0 . 4 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 2 . 7 5 0 . 1 5 + 0 . 3 5 0 . 8 0 . 2 0 . 1 5 0 . 0 5 + 0 . 1 8 0 p i n q f p ( p l a s t i c ) m 0 . 2 0 . 1 5 0 t o 1 0 d e t a i l a a s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 a l l o y p a c k a g e s t r u c t u r e 1 4 . 0 0 . 2 * 1 2 . 0 0 . 1 ( 0 . 2 2 ) 6 0 4 1 4 0 2 1 2 0 8 0 6 1 1 0 . 1 8 0 . 0 3 + 0 . 0 8 a 1 . 5 0 . 1 + 0 . 2 0 . 1 2 7 0 . 0 2 + 0 . 0 5 0 . 5 0 . 2 ( 1 3 . 0 ) 0 . 1 0 . 1 0 . 5 0 . 2 0 t o 1 0 d e t a i l a 8 0 p i n l q f p ( p l a s t i c ) 0 . 5 g l q f p - 8 0 p - l 0 1 l q f p 0 8 0 - p - 1 2 1 2 0 . 1 n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 1 3 m 0 . 5 cxp83620/83624
? 30 cxp83620/83624, cxp83621/83625 cxp83621/83625 s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y q f p - 8 0 p - l 0 3 q f p 0 8 0 - p - 1 4 1 4 0 . 6 g 8 0 p i n q f p ( p l a s t i c ) 1 6 . 0 0 . 4 1 4 . 0 0 . 1 + 0 . 4 0 . 3 0 . 1 + 0 . 1 5 0 t o 1 0 0 . 5 0 . 2 0 . 1 0 . 1 + 0 . 1 5 ( 1 5 . 0 ) 0 . 1 2 7 0 . 0 5 + 0 . 1 1 . 5 0 . 1 5 + 0 . 3 5 4 0 2 1 2 0 1 4 1 6 0 6 1 8 0 m 0 . 2 4 0 . 1 0 . 6 5

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